The electronics industry continues to strive for high-powered, high-functioning circuits. Significant achievements in this regard have been realized through the fabrication of very large-scale integration of circuits on small areas of silicon wafer. These complex circuits are often designed as functionally-defined modules that operate on a set of data and then pass that data on for further processing. This communication from such functionally-defined modules can be passed in small or large amounts of data between individual discrete circuits, between integrated circuits within the same chip, and between remotely-located circuits coupled to or within various parts of a system or subsystem. Regardless of the configuration, the communication typically requires closely-controlled interfaces to insure that data integrity is maintained and that circuit designs are sensitive to practicable limitations in terms of implementation space and available operating power.
The demand for high-powered, high-functioning semiconductor devices has lead to an ever-increasing demand for accelerating the speed at which data is passed between the circuit blocks. Many of these high-speed communication applications can be implemented using parallel data transmission in which multiple data bits are simultaneously sent across parallel communication paths. Such “parallel bussing” is a well-accepted approach for achieving data transfers at high data rates. For a given data-transmission rate (sometimes established by a clock passed along with the data), the bandwidth, measured in bits-per-second, is equivalent to the data transmission rate times the number of data signals comprising the parallel data interconnect.
A typical system might include a number of modules that interface to and communicate over a parallel data communication line (sometimes referred to as a data channel); for example, in the form of a cable, a backplane circuit, a bus structure internal to a chip, other interconnect, or any combination of such communication media. A sending module would transmit data over the bus synchronously with a clock on the sending module. In this manner, the transitions over the parallel signal lines leave the sending module in a synchronous relationship with each other and/or to the clock on the sending module. At the other end of the parallel data interconnect, the data is received along with a clock signal; the receive clock is typically derived from or is synchronous with the clock on the sending module. The rate at which the data is passed over the parallel signal lines is sometimes referred to as the (parallel) “bus rate.”
In such systems, it is beneficial to ensure that the received signals (and where applicable, the receive clock) have a specific phase relationship to the transmit clock, to provide proper data recovery. There is often an anticipated amount of time “skew” between the transmitted data signals themselves and between the data signals and the receive clock at the destination. There are many sources of skew including, for example, transmission delays introduced by the capacitive and inductive loading of the signal lines of the parallel interconnect, variations in the I/O (input/output) driver source, intersymbol interference and variations in the transmission lines' impedance and length. Regardless of which phenomena cause the skew, achieving communication with proper data recovery, for many applications, should take this issue into account.
For parallel interconnects serving higher-speed applications, in connection herewith it has been discovered that skew is “pattern dependent” and that the severity of this issue can be mitigated and, in many instances, largely overcome. As described in the above-referenced patent document entitled “Parallel Communication Based On Balanced Data-Bit Encoding” (VLSI.295PA), this pattern dependency results from the imperfect current sources shared between the data bits in the parallel bus. The shared current sources induce skew at the driver, which directly reduces margin at the receiver, which in turn can cause data transmission errors.
Many of these high-speed parallel communication applications require a voltage-biased termination at the receiving end. The voltage-biased termination minimizes discontinuities at communication-media junctions as can occur with most high-frequency signaling implementations, and also provides an appropriate signal level when the parallel communication bus is idle. Because these goals are directed to preserving signal integrity for the overall communication process, many industry recommendations include specific requirements for the type and location of the termination.
These bus terminations are typically implemented to draw power. For instance, the SST—2 signaling described in EIA/JEDEC Standard STUB Series Terminated Logic For 2.5 Volts (SSTL—2), EIA/JESD8-9 suggests a biased termination that would be typically implemented using a resistor for each bus line, with one resistor end connected to the bus line and the other end connected to a voltage-reference node. Unfortunately, using the voltage-reference node to bias the bus line constantly consumes power and for an application with a parallel data bus involving a large number of bus lines, the magnitude of power consumed increases accordingly.
This power consumption concern can be mitigated to a degree by switching off the termination power when the bus is in an idle state. This approach, however, can adversely effect throughput and thereby degrade bus performance. In addition, switching off the termination power in such a manner requires a switching control circuit, which also consumes power.
For high-speed data-transmission applications, there are various other disadvantages. For example, many interfaces are designed without sufficient consideration of the space and material costs in the number of power nodes and conductors required for passing such high-speed data signals over the parallel busses. By reducing the power consumption for such high-speed applications, the number of power nodes and conductor pins can be reduced; in a power-critical application, such reductions can be significant. Moreover, reducing the current flow in high-speed parallel data communication applications can substantially reduce electromagnetic interference (“EMI”) which, in turn, can reduce the likelihood of signal recovery problems at the receiving module and thereby reduce the need for expensive and often burdensome EMI shielding.
Accordingly, improving data communication over parallel busses permits more practicable and higher-speed parallel bussing applications which, in turn, can directly lead to higher-powered, higher-functioning circuits that preserve data integrity and are sensitive to needs for reducing implementation space and power consumption.